View CS5525-BP_553991.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CS5525 CS5526
16-Bit/20-Bit Multi-Range ADC with 4-Bit Latch
Features
Delta-Sigma A/D Converter
- Linearity Error: 0.0015%FS - Noise Free Resolution: 18-bits
General Description
The 16-bit CS5525 and the 20-bit CS5526 are highly integrated A/D converters which include an instrumentation amplifier, a PGA (programmable gain amplifier), eight digital filters, and self and system calibration circuitry. The converters are designed to provide their own negative supply which enables their on-chip instrumentation amplifiers to measure bipolar ground-referenced signals 100 mV. By directly supplying NBV with -2.5 V and with VA+ at 5 V, 2.5 V signals (with respect to ground) can be measured. The digital filters provide programmable output update rates between 3.76 Hz to 202 Hz (XIN = 32.768 kHz). Output word rates can be increased by approximately 3X by using XIN = 100 kHz. Each filter is designed to settle to full accuracy for its output update rate in one conversion cycle. The filters with word rates of 15 Hz or less (XIN = 32.768 kHz) reject both 50 and 60 Hz (3 Hz) line interference simultaneously. Low power, single conversion settling time, programmable output rates, and the ability to handle negative input signals make these single supply products ideal solutions for isolated and non-isolated applications. ORDERING INFORMATION See page26.
Bipolar/Unipolar Input Ranges
- 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V
Chopper Stabilized Instrumentation Amplifier On-Chip Charge Pump Drive Circuitry 4-Bit Output Latch Simple three-wire serial interface
- SPITM and MicrowireTM Compatible - Schmitt Trigger on Serial Clock (SCLK)
Programmable Output Word Rates
- 3.76 Hz to 202Hz (XIN = 32.768 kHz) - 11.47 Hz to 616 Hz (XIN = 100 kHz)
Output Settles in One Conversion Cycle Simultaneous 50/60 Hz Noise Rejection System and Self-Calibration with Read/Write Registers Single +5 V Analog Supply +3.0 V or +5 V Digital Supply Low Power Mode Consumption: 4.9 mW
- 1.8 mW in 1 V, 2.5 V, and 5 V Input Ranges
VA+
AGND
VREF+
VREF-
DGND
VD+
AIN+ AIN-
+ X20 -
Programmable Gain
Differential 4th Order Delta-Sigma Modulator
Digital Filter
Calibration Register
CS SCLK
NBV A0 A1 A2 A3
Control Register
SDI
Latch Calibration Memory Calibration C Clock Gen.
Output Register
SDO
CPD
XIN XOUT
Cirrus Logic, Inc. www.cirrus.com
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
Nov `03 DS202F3 1
CS5525 CS5526
(TA = 25 C; VA+, VD+ = 5 V 5%; VREF+ = 2.5 V, VREF- = AGND, NBV = -2.1 V, FCLK = 32.768 kHz, OWR (Output Word Rate) = 15 Hz, Bipolar Mode, Input Range = 100 mV; See Notes 1 and 2.) CS5525 Parameter Min 16 (Note 3) (Note 3) (Notes 3 and 4) (Note 4) (VREF+) - (VREF-) dc 50, 60 Hz (Note 5) 1 Typ Max Min 20 1 CS5526 Typ Max Unit %FS Bits LSB LSB nV/C ppm ppm ppm/C V dB dB pF A/V
ANALOG CHARACTERISTICS
Accuracy Linearity Error
No Missing Codes Bipolar Offset Unipolar Offset Offset Drift Bipolar Gain Error Unipolar Gain Error Gain Drift
0.0015 0.003 1 2 20 8 16 1 2.5 110 130 16 0.6 2 4 31 62 3 3.0 -
0.0007 0.0015 16 32 20 8 16 1 2.5 110 130 16 0.6 32 64 31 62 3 3.0 -
Voltage Reference Input
Range Common Mode Rejection Input Capacitance CVF Current
Notes: 1. Applies after system calibration at any temperature within -40 C ~ +85 C. 2. Specifications guaranteed by design, characterization, and/or test. 3. Specification applies to the device only and does not include any effects by external parasitic thermocouples. LSB = LSB 16 for the CS5525, and LSB20 for the CS5526. 4. Drift over specified temperature range after calibration at power-up at 25 C. 5. See the section of the data sheet which discusses input models on page 15.
RMS NOISE (Notes 6 and 7)
Output Rate (Hz) 3.76 7.51 15.0 30.1 60.0 123.2 (Note 8) 168.9 (Note 8) 202.3 (Note 8) -3 dB Filter Frequency 3.27 6.55 12.7 25.4 50.4 103.6 141.3 169.2 25 mV 90 nV 110 nV 170 nV 250 nV 500 nV 2.0 V 10 V 30 V Input Range, (Bipolar/Unipolar Mode) 55 mV 100 mV 1V 2.5 V 90 nV 130 nV 1.0 V 2.0 V 130 nV 190 nV 1.5 V 3.0 V 200 nV 250 nV 2.0 V 5.0 V 300 nV 500 nV 4.0 V 10 V 1.0 V 1.5 V 15 V 45 V 4.0 V 8.0 V 72 V 190 V 20.0 V 30 V 340 V 900 V 55 V 105 V 1.1 mV 2.4 mV 5V 4.0 V 7 V 10 V 15 V 85 V 350 V 2.0 mV 5.3 mV
Notes: 6. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 C. 7. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates. 8. For input ranges <100 mV and output word rates >60 Hz, 32.768 kHz chopping frequency is used. Specifications are subject to change without notice.
2
DS202F3
CS5525 CS5526
ANALOG CHARACTERISTICS (Continued)
Parameter Min Typ Max Unit
Analog Input
Common Mode + Signal on AIN+ or AINBipolar/Unipolar Mode NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V NBV = AGND Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V Common Mode Rejection Input Capacitance CVF Current on AIN+ or AIN(Note 5) Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V dc 50, 60 Hz -0.150 NBV 1.85 0.0 120 120 10 100 1.2 0.950 VA+ 2.65 VA+ 300 V V V V dB dB pF pA A/V
System Calibration Specifications Full Scale Calibration Range 25 mV 55 mV 100 mV 1V 2.5 V 5V
Offset Calibration Range 25 mV 55 mV 100 mV 1V 2.5 V 5V
Bipolar/Unipolar Mode (Note 9) 17.5 38.5 70 0.70 1.75 3.50 Bipolar/Unipolar Mode 1.65 15 475 9.4 4.9 1.2 500 95 110 12.5 27.5 50 0.5 1.25 2.50 2.2 30 700 12.7 8.5 mV mV mV V V V mA A A mW mW mW W dB dB 32.5 71.5 105 1.30 3.25 VA+ mV mV mV V V V
(Note 10)
Power Supplies
DC Power Supply Currents (Normal Mode) IA+ ID+ INBV Power Consumption Normal Mode Low Power Mode Standby Sleep dc Positive Supplies dc NBV (Note 11)
Power Supply Rejection
Notes: 9. The minimum Full Scale Calibration Range (FSCR) is limited by the maximum allowed gain register value (with margin). The maximum FSCR is limited by the modulator's 1's density range. 10. The maximum full scale signal can be limited by saturation of circuitry within the internal signal path. 11. All outputs unloaded. All input CMOS levels.
DS202F3
3
CS5525 CS5526
5 V DIGITAL CHARACTERISTICS (TA = 25 C; VA+, VD+ = 5 V 5%; GND = 0;
See Notes 2 and 12.)) Parameter High-Level Input Voltage All Pins Except XIN and SCLK XIN SCLK All Pins Except XIN and SCLK XIN SCLK Symbol VIH Min 0.6 VD+ 3.5 (VD+) - 0.45 0.0 (VA+) - 1.0 (VD+) - 1.0 (VD+) - 1.0 VOL Iin IOZ Cout 1 9 0.4 0.4 0.4 10 10 V V V A A pF Typ Max VD+ 0.8 1.5 0.6 Unit V V V V V V V V V
Low-Level Input Voltage
VIL
High-Level Output Voltage All Pins Except CPD and SDO (Note 13) CPD, Iout = -4.0 mA SDO, Iout = -5.0 mA Low-Level Output Voltage All Pins Except CPD and SDO, Iout = 1.6 mA CPD, I out = 2 mA SDO, Iout = 5.0 mA Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance Notes: 12. All measurements performed under static conditions.
VOH
13. Iout = -100 A unless stated otherwise. (V OH = 2.4 V @ Iout = -40 A.)
3.0 V DIGITAL CHARACTERISTICS (TA = 25 C; VA+ = 5 V 5%; VD+ = 3.0 V 10%; GND = 0;
See Notes 2 and 12.)) Parameter High-Level Input Voltage All Pins Except XIN and SCLK XIN SCLK All Pins Except XIN and SCLK XIN SCLK Symbol VIH Min 0.6 VD+ 0.54 VA+ (VD+) - 0.45 0.0 (VA+) - 0.3 (VD+) - 1.0 (VD+) - 1.0 VOL Iin IOZ Cout 1 9 0.3 0.4 0.4 10 10 V V V A A pF Typ Max VD+ 0.16 VD+ 1.5 0.6 Unit V V V V V V V V V
Low-Level Input Voltage
VIL
High-Level Output Voltage All Pins Except CPD and SDO, Iout = -400 A CPD, Iout = -4.0 mA SDO, Iout = -5.0 mA Low-Level Output Voltage All Pins Except CPD and SDO, Iout = 400 A CPD, I out = 2 mA SDO, Iout = 5.0 mA Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance
VOH
4
DS202F3
CS5525 CS5526
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Filter Settling Time to 1/2 LSB (Full Scale Step) Symbol fs ts Ratio XIN/2 1/fout Unit Hz s
RECOMMENDED OPERATING CONDITIONS
Parameter DC Power Supplies Analog Reference Voltage Negative Bias Voltage Notes: 14. All voltages with respect to ground. Positive Digital Positive Analog (VREF+) - (VREF-)
(AGND, DGND = 0 V; See Note 14.)) Min 2.7 4.75 1.0 -1.8 Typ 5.0 5.0 2.5 -2.1 Max 5.25 5.25 3.0 -2.5 Unit V V V V
Symbol VD+ VA+ VRefdiff NBV
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; See Note 14.)
Parameter DC Power Supplies (Note 15) Positive Digital Positive Analog Negative Potential (Note 16 and 17) (Note 18) VREF pins AIN Pins Symbol VD+ VA+ NBV IIN IOUT PDN VINR VINA VIND TA Tstg Min -0.3 -0.3 +0.3 -0.3 NBV - 0.3 -0.3 -40 -65 Max +6.0 +6.0 -3.0 10 25 500 (VA+) + 0.3 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V V mA mA mW V V V C C
Negative Bias Voltage Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: 15. No pin should go more negative than NBV - 0.3 V. 16. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins. 17. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is 50 mA. 18. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
DS202F3
5
CS5525 CS5526
(TA = 25 C; VA+ = 5 V 5%; VD+ = 3.0 V 10% or 5 V 5%; Input Levels: Logic 0 = 0 V, Logic 1 = VD+; C L = 50 pF.)) Parameter Master Clock Frequency (Note 19) Internal Clock External Clock (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output XTAL = 32.768 kHz (Note 21) Symbol XIN 30 30 40 trise tfall tost tpor 50 500 1003 1.0 100 s s ns ms XIN cycles MHz ns ns ns 50 1.0 100 s s ns 32.768 32.768 36 100 60 kHz % Min Typ Max Unit
SWITCHING CHARACTERISTICS
Master Clock Duty Cycle Rise Times
Fall Times
Start-up Oscillator Start-up Time
Power-on Reset Period
Serial Port Timing Serial Clock Frequency
SCLK Falling to CS Falling for continuous running SCLK (Note 22) Serial Clock Pulse Width High Pulse Width Low
SCLK t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
0 100 250 250
-
2 -
SDI Write Timing
CS Enable to Valid Latch Clock Data Set-up Time prior to SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior to CS Disable 50 50 100 100 150 150 150 ns ns ns ns ns ns ns
SDO Read Timing
CS to Data Valid SCLK Falling to New Data Bit CS Rising to SDO Hi-Z
Notes: 19. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 100 kHz can be used for increased throughput. 20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. 22. Applicable when SCLK is continuously running.
6
DS202F3
CS5525 CS5526
CS
t0
t3
t1
t6
SCLK
t2
Continuous Running SCLK Timing (Not to Scale)
CS
t3
SDI
M SB
t4
M S B -1
t5 t1
LS B
t6
S C LK
t2
SDI Write Timing (Not to Scale)
CS
t7 t9
SDO
MSB
t8
M S B-1
t2
LSB
S C LK
t1
SDO Read Timing (Not to Scale)
DS202F3
7
CS5525 CS5526
DETAILED DESCRIPTION
The CS5525 and CS5526 are 16-bit and 20-bit pin compatible converters which include a chopperstabilized instrumentation amplifier input, and an on-chip programmable gain amplifier. They are both optimized for measuring low-level unipolar or bipolar signals in process control and medical applications. The CS5525/26 also include a fourth order deltasigma modulator, a calibration microcontroller, eight digital filters, a 4-bit analog latch, and a serial port. The digital filters provide any one of eight different output update rates. The CS5525/26 include a CPD (Charge Pump Drive) output (shown in Figure 1). CPD provides a negative bias voltage to the on-chip instrumentation amplifier when used with a combination of external diodes and capacitors. This enables the CS5525/26 to measure negative voltages with re+ 5V A n alo g S u pp ly
spect to ground, making the converters ideal for thermocouple temperature measurements.
Theory of Operation
The CS5525/26 A/D converters are designed to operate from a single +5 V analog supply and provide several different input ranges. See the Analog Characteristics section on page 3 for details. Figure 1 illustrates the CS5525/26 connected to generate their own negative bias supply using the on-chip CPD (Charge Pump Drive). This enables the CS5525/26 to measure ground referenced signals with magnitudes down to NBV (Negative Bias Voltage, approximately -2.1 V in this example). Figure 2 illustrates a charge pump circuit when the converters are powered from a +3.0 V digital supply. Alternatively, the negative bias supply can be generated from a negative supply voltage or a resistive divider as illustrated in Figure 3.
10
0 .1 F
0 .1 F
2 VA+ 2 .5 V 20 19 U p to 1 0 0 m V In p u t 10 k BAV199 0 .1 F 10 k N o te : C o ld-ju n c tio n m e a s u re m en t is p e rform ed b y a s e c o n d A /D o r v ia a m u ltip le x e r. L o g ic O u tp u ts : A 0 - A 3 S w itc h fro m V A + to A G N D . 4 A IN 1 AGND 16 A3 15 A2 7 A1 6 A0 NBV 5 V R E F+ VREF-
13 VD+ XO UT 10 50 0k 20 p F
32 .76 8 ~ 100 kH z 3
C S5 5 25 C S 55 26
X IN
9
A IN + CS S C LK SDI SDO
O p tio n a l C lo c k S o u rc e
18 11 17 14 S e ria l D ata In te rfa ce
C PD DG N D 12 8
*5 M
* O p tio n a l, s e e C h a rg e P u m p D riv e s e c tio n .
1N4148 10 F
0 .0 1 5 F
+
1N4148
C h a rg e -p u m p n e tw o rk fo r V D + = 5 V o n ly a n d X IN = 3 2 .7 6 8 k H z .
Figure 1. CS5525/26 Configured to use on-chip charge pump to supply NBV.
8
DS202F3
CS5525 CS5526
Figure 4 illustrates the CS5525/26 connected to measure ground referenced unipolar signals of a positive polarity using the 1 V, 2.5 V, and 5 V input voltage ranges on the converter. For the 25 mV, 55 mV, and 100 mV ranges the signal must have a common mode near +2.5 V (NBV = 0V). The CS5525/26 are optimized for the measurement of thermocouple outputs, but they are also well suited for the measurement of ratiometric bridge transducer outputs. Figure 5 illustrates the CS5525/26 connected to measure the output of a ratiometric differential bridge transducer while operating from a single +5 V supply.
2N 5 0 87 o r sim ila r N BV + 1 0 F
3 4 .8 K N BV 3 0 .1 K
2 .0 K
+
1 0 F
2 .1 K
-5 V
-5 V
Figure 2. Charge Pump Drive Circuit for VD+ = 3 V.
Figure 3. Alternate NBV Circuits.
+ 5V A nalo g S upply
10 0 .1 F 2 VA+ 2.5V 20 19 V R E F+ V R EF C S5525 C S 55 2 6
0 .1 F 13 VD+ XO U T 10 500k 20 p F
X IN
9
3 0 to + 5V Input
A IN +
32.768 ~ 100kH z O ptional C loc k S ourc e
+ C M = 0 to V A +
CS 4 A IN 1 S C LK AG ND 16 A3 SDI 15 A2 7 SDO A1 6 A0 N BV C PD D G N D 5 8 12
18 11 17 14 S e rial D ata Interface
Figure 4. CS5525/26 Configured for ground-referenced Unipolar Signals.
DS202F3
9
CS5525 CS5526
+5V A nalog S upply
10 0.1 F 2 VA+ 20 19 VR E F+ VR E FAIN +
C S5 5 25 C S 5 52 6
0.1 F 13 VD+ X OU T 10 500k 20 pF
-
30 m V F.S .
+
3
X IN
9
32.768 ~ 100kH z O ptional C loc k S ource
CS 4 AIN S CLK 1 AG ND 16 A3 S DI 15 A2 S DO 7 A1 6 A0 N B V C PD DG ND 5 8 12
18 11 17 14 S e rial D ata In te rface
Figure 5. CS5525/26 Configured for Single Supply Bridge Measurement.
System Initialization
When power to the CS5525/26 is applied, they are held in a reset condition until their 32.768 kHz oscillators have started and their start-up counter-timer elapses. Due to the high Q of a 32.768 kHz crystal, the oscillators take 400-600 ms to start. The converter's counter-timer counts no more than 1024 oscillator clock cycles to make sure the oscillator is fully stable. During this time-out period the serial port logic is reset and the RV (Reset Valid) bit in the configuration register is set. A reset can be initiated at any time by writing a logic 1 to the RS (Reset System) bit in the configuration register. This automatically sets the RV bit until the RS bit is written to logic 0, and the configuration register is read. After a reset, the on-chip registers are initialized to the following states and the converters are ready to perform conversions.
configuration register: offset register: gain register: 000040(H) 000000(H) 800000(H)
Command Operation
The CS5525/26 include a microcontroller with five registers used to control the converter. Each register is 24-bits in length except the 8-bit command register (command, configuration, offset, gain, and conversion data). After a system initialization or reset, the serial port is initialized to the command mode and the converter stays in this mode until a valid 8-bit command is received (the first 8-bits into the serial port). Table 1 lists all the valid commands. Once a valid 8-bit command (a read or a write command word) is received and interpreted by the command register, the serial port enters the data mode. In data mode the next 24 serial clock pulses shift data either into or out of the serial port (72 serial clock pulses are needed if set-up register is selected). See Table 2 for configuring the CS5525/26.
10
DS202F3
CS5525 CS5526
Reading/Writing On-Chip Registers
The CS5525/26's offset, gain, and configuration registers are read/writable while the conversion data register is read only. To perform a read from a specific register, the R/W bit of the command word must be a logic 1. The SC, CC, and PS/R bits must be logic 0 and the CB (MSB) bit must be a logic 1. The register to be written is selected with the RSB2-RSB0 bits of the command word. To perform a write to a specific register, the R/W bit of the command word must be a logic 0. The SC, CC, and PS/R bits must be logic 0 and the CB (MSB) bit must be a logic 1. The register to be written is selected with the RSB2-RSB0 bits of the command word. Figure 6 illustrates the serial sequence necessary to write to, or read from the serial port. If the Set-up Registers are chosen with the RSB2RSB0 bits, the registers are read or written in the following sequence: Offset, Gain and Configuration. This is accomplished by following one 8-bit command word with three 24-bit data words for a total of 72 data bits.
Command Register
D7(MSB) CB BIT D7 D6 SC D5 CC NAME Command Bit, CB D4 R/W D3 RSB2 VALUE 0 1 D6 D5 D4 D3-D1 Single Conversion, SC Continuous Conversions, CC Read/Write, R/W Register Select Bit, RSB2-RSB0 0 1 0 1 0 1 000 001 010 011 100 101 110 111 0 1 D2 RSB1 D1 RSB0 D0 PS/R FUNCTION Null command (no operation). All command bits, including CB must be 0. Logic 1 for executable commands. Single Conversion not active. Perform a conversion. Continuous Conversions not active. Perform conversions continuously. Write to selected register. Read from selected register. Offset Register Gain Register Configuration Register Conversion Data Register (read only) Set-up Registers (Offset, Gain, Configuration) Reserved Reserved Reserved Run Power Save
D0
Power Save/Run, PS/R
Table 1. Command Set
DS202F3
11
CS5525 CS5526
Configuration Register
D23(MSB) A3 D11 G2 BIT D23-D20 D19 D18 D17 D16 D15-D13 D22 A2 D10 G1 D21 A1 D9 G0 NAME Latch Outputs, A3-A0 Not Used, NU Chop Frequency Select, CFS Not Used, NU Low Power Mode, LPM Word Rate, WR2-0 Note: For XIN = 32.768kHz D20 A0 D8 PD VALUE 0000 0 0 1 0 0 1 000 001 010 011 100 101 110 111 0 1 000 001 010 011 100 101 110/111 0 1 0 1 0 1 0 1 0 1 0 1 000 001 010 011 100 101 110 111 R Must always be logic 0. R 256 Hz Amplifier chop frequency 32768 Hz Amplifier chop frequency R Must always be logic 0. R Normal Mode Reduced Power mode R 15.0 Hz (2182 XIN cycles) 30.1 Hz (1090 XIN cycles) 60.0 Hz (546 XIN cycles) 123.2 Hz (266 XIN cycles) 168.9 Hz (194 XIN cycles) 202.3 Hz (162 XIN cycles) 3.76 Hz (8722 XIN cycles) 7.51 Hz (4362 XIN cycles) R Bipolar Measurement mode Unipolar Measurement mode R 100 mV (assumes VREF = 2.5V) 55 mV 25 mV 1V 5.0 V 2.5 V Not Used. R Charge Pump Enabled For PD = 1, the CPD pin goes to a Hi-Z output state. R Normal Operation Activate a Reset cycle. To return to Normal Operation write bit to zero. No reset has occurred or bit has been cleared (read only). R Valid Reset has occurred. (Cleared when read.) R Port Flag mode inactive Port Flag mode active R Standby Mode (Oscillator active, allows quick power-up) Sleep Mode (Oscillator inactive) R Done Flag bit is cleared (read only). Calibration or Conversion cycle completed (read only). R Normal Operation (no calibration) Offset -- Self-Calibration Gain -- Self-Calibration Offset Self-Calibration followed by Gain Self-Calibration Not used. Offset -- System Calibration Gain -- System Calibration Not Used. D19 NU D7 RS D18 CFS D6 RV D17 NU D5 PF D16 LPM D4 PSS D15 WR2 D3 DF FUNCTION R* Latch Output Pins A3-A0 mimic the D23-D20 Register bits. D14 WR1 D2 CC2 D13 WR0 D1 CC1 D12 U/B D0 CC0
D12 D11-D9
Unipolar/Bipolar, U/B Gain Bits, G2-G0
D8 D7 D6 D5 D4 D3 D2-D0
Pump Disable, PD Reset System, RS Reset Valid , RV Port Flag, PF Power Save Select, PSS Done Flag, DF Calibration Control Bits, CC2-CC0
* R indicates the bit value after the part is reset Table 2. Configuration Register 12 DS202F3
CS5525 CS5526
CS
SCLK
SDI C om m a n d T im e 8 SC L Ks
MSB
LSB
D a ta T im e 2 4 SC L K s (o r 7 2 S C L K s fo r S e t-u p R e g iste rs) W rite C y c le
CS
SCLK
SDI C om m a n d T im e 8 SC L Ks SDO
MSB LSB
D a ta T im e 2 4 S C L K s (o r 7 2 S C L K s fo r S et-u p R e g iste rs ) R ea d C yc le
S CLK
SDI C om m a n d T im e 8 SC LKs SD O * td = X IN /O W R clo ck cycles fo r each conversion exce pt the first conversion w hich w ill take XIN/O W R + 7 clock cycles SDO C ontinu ous C onversion R ead (PF b it = 1) td * X IN /O W R C lo ck C yc le s 8 S C L K s C le a r S D O Fla g
MSB LSB
D ata T im e 24 SC LK s
Figure 6. Command and Data Word Timing.
DS202F3
13
CS5525 CS5526
Analog Input
Figure 7 illustrates a block diagram of the analog input signal path inside the CS5525/26. The front end consists of a chopper-stabilized instrumentation amplifier with 20X gain and a programmable gain section. The instrumentation amplifier is powered from VA+ and from the NBV (Negative Bias Voltage) pin allowing the CS5525/26 to be operated in either of two analog input configurations. The NBV pin can be biased to a negative voltage between -1.8 V and -2.5 V, or tied to AGND. The choice of the operating mode for the NBV voltage depends upon the input signal and its common mode voltage. For the 25 mV, 55 mV, and 100 mV input ranges, the input signals to AIN+ and AIN- are amplified by the 20X instrumentation amplifier. For ground referenced signals with magnitudes less then 100 mV, the NBV pin should be biased with -1.8 V to -2.5 V. If NBV is tied between -1.8 V and -2.5 V, the (Common Mode + Signal) input on AIN+ and AIN- must stay between -0.150 V and 0.950 V to ensure proper operation. Alternatively, NBV can be tied to AGND where the input (Common Mode + Signal) on AIN+ and AIN- must stay between 1.85 V and 2.65 V to ensure that the amplifier operates properly. For the 1 V, 2.5 V, and 5 V input ranges, the instrumentation amplifier is bypassed and the input signals are directly connected to the Programmable Gain block. With NBV tied between -1.8 V and -2.5 V, the (Common Mode + Signal) input on AIN+ and AIN- must stay between NBV and VA+. Alternatively, NBV can be tied to AGND where the input (Common Mode + Signal) on AIN+ and AIN- pins can span the entire range between AGND and VA+. The CS5525/26 can accommodate full scale ranges other than 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V by performing a system calibration within the limits specified. See the Calibration section for more details. Another way to change the full scale range is to increase or to decrease the voltage reference to other than 2.5 V. See the Voltage Reference section for more details. Three factors set the operating limits for the input span. They include: instrumentation amplifier saturation, modulator 1's density, and a lower reference voltage. When the 25 mV, 55 mV or 100 mV range is selected, the input signal (including the common mode voltage and the amplifier offset voltage) must not cause the 20X amplifier to saturate in either its input stage or output stage. To prevent saturation the absolute voltages on AIN+ and AINmust stay within the limits specified (refer to the `Analog Input' table on page 3). Additionally, the differential output voltage of the amplifier must not exceed 2.8 V. The equation ABS(VIN + VOS) x 20 = 2.8 V defines the differential output limit, where VIN = (AIN+) - (AIN-) is the differential input voltage and VOS is the absolute maximum offset voltage for the instrumentation amplifier (VOS will not exceed 40 mV). If the
VREF+ VREF-
A IN + A IN NBV
X 20
P ro g ra m m a b le G a in
D iffe re n tia l 4 th o rd er d e lta s ig m a m o d u la to r
D ig ita l F ilter
Figure 7. Block Diagram of Analog Signal Path 14 DS202F3
CS5525 CS5526
- Nominal (1) Differential Input 0.5 V 1.1 V 2.0 V 1.0 V 2.5 V 5.0 V -(1) Max. Input 0.75 V 1.65 V 3.0 V 1.5 V 5.0 V 0V, VA+
Input Range(1) 25 mV 55 mV 100 mV 1.0 V 2.5 V 5.0 V
Max. Differential Output 20X Amplifier 2.8 V (2) 2.8 V
(2)
VREF 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
Gain Factor 5 2.272727... 1.25 2.5 1.0 0.5
2.8 V (2) -
Note:
1. The converter's actual input range, the delta-sigma's nominal full scale input, and the delta-sigma's maximum full scale input all scale directly with the value of the voltage reference. The values in the table assume a 2.5 V VREF voltage. Table 3. Relationship between Full Scale Input, Gain Factors, and Internal Analog Signal Limitations
differential output voltage from the amplifier exceeds 2.8 V, the amplifier may saturate, which will cause a measurement error. The input voltage into the modulator must not cause the modulator to exceed a low of 20 percent or a high of 80 percent 1's density. The nominal full scale input span of the modulator (from 30 percent to 70 percent 1's density) is determined by the VREF voltage divided by the Gain Factor. See Table 3 to determine if the CS5525/26 are being used properly. For example, in the 55 mV range to determine the nominal input voltage to the modulator, divide VREF (2.5 V) by the Gain Factor (2.2727). When a smaller voltage reference is used, the resulting code widths are smaller causing the converter output codes to exhibit more changing codes for a fixed amount of noise. Table 3 is based upon a VREF = 2.5 V. For other values of VREF, the values in Table 3 must be scaled accordingly. Figure's 8 and 9 illustrate the input models for the AIN and VREF pins. The dynamic input current for each of the pins can be determined from the models shown and is dependent upon the setting of the CFS (Chop Frequency Select) bit. The effective input impedance for the AIN+ and AIN- pins remains constant for the three low level measurement ranges (25 mV, 55 mV, and 100 mV). The input current is lowest with the CFS bit cleared to logic 0.
DS202F3
Note: Residual noise appears in the converter's baseband for output word rates greater than 60 Hz if CFS is logic 0. By setting CFS to logic 1, the amplifier's chop frequency chops at 32768 Hz eliminating the residual noise, but increasing the current. Note that C=48pF is for input current modeling only. For physical input capacitance see `Input Capacitance' specification under `Analog Characteristics' on page 3.
25m V, 55m V , and 100m V R anges
AIN V os 25 m V i n = fV os C
C = 48pF
CF S = 0 , f = 256 Hz CF S = 1 , f = 32.7 68 kH z
1V, 2.5 V, and 5V Ran ges
A IN+ AINC = 3 2pF
i n = [(V A IN + ) - (V A IN - )] fC
f = 32.76 8 kH z Figure 8. Input models for AIN+ and AIN- pins
VR E F + VREFC = 16 pF
i n = [(V R E F + ) - (V R EF -)] fC f = 3 2.7 68 k H z
Figure 9. Input model for VREF+ and VREF- pins.
15
CS5525 CS5526
Charge Pump Drive
The CPD (Charge Pump Drive) pin of the converters can be used with external components (shown in Figure 1) to develop an appropriate negative bias voltage for the NBV pin. When CPD is used to generate the NBV, the NBV voltage is regulated with an internal regulator loop referenced to VA+. Therefore, any change on VA+ results in a proportional change on NBV. With VA+ = 5 V, NBV's regulation is set proportional to VA+ at approximately -2.1 V. Figure 3 illustrates a means of supplying NBV voltage from a -5 V supply. For ground based signals with the instrumentation amplifier engaged (when in the 25mV, 55mV, or 100mV ranges), the voltage on the NBV pin should at no time be less negative than -1.8 V or more negative than -2.5 V. To prevent excessive voltage stress to the chip the NBV voltage should not be more negative than -3.0 V. The components in Figure 1 are the preferred components for the CPD filter. However, smaller capacitors can be used with acceptable results. The 10 F ensures very low ripple on NBV. Intrinsic safety requirements prohibit the use of electrolytic capacitors. In this case, two 0.47 F ceramic capacitors in parallel can be used. The CPD pin itself is a tri-state output and enters tri-state whenever the converters are placed into the Sleep Mode, Standby Mode, or when the charge pump is disabled (when the Pump Disable bit, bit D8 in the configuration register, is set). Once in tristate, the digital current can increase if this CPD output floats near 1/2 digital supply. To ensure the CPD pin stays near ground and to minimize the digital current, add a 5M resistor between it and DGND (see Figure 1). If the resistor is left out, the digital supply current may increase from 2 A to 10 A.
Voltage Reference
The CS5525/26 are specified for operation with a 2.5 V reference voltage between the VREF+ and VREF- pins of the devices. For a single-ended reference voltage, such as the LT1019-2.5, the reference's output is connected to the VREF+ pin of the CS5525/26. The ground reference for the LT10192.5 is connected to the VREF- pin. The differential voltage between the VREF+ and VREF- can be any voltage from 1.0 V up to 3.0 V, however, the VREF- pin can not go below analog ground.
Calibration
The CS5525/26 offer five different calibration functions including self calibration and system calibration. However, after the CS5525/26 are reset, they can perform measurements without being calibrated. In this case, the converters will utilize the initialized values of the on-chip registers (Gain = 1.0, Offset = 0.0) to calculate output words for the 100 mV range. Any initial offset and gain errors in the internal circuitry of the chips will remain. The gain and offset registers, which are used for both self and system calibration, are used to set the zero and full-scale points of the converter's transfer function. One LSB in the offset register is 2-24 proportion of the input span (bipolar span is 2 times the unipolar span). The MSB in the offset register determines if the offset to be trimmed is positive or negative (0 positive, 1 negative). The converters can typically trim 50 percent of the input span. The gain register spans from 0 to (2 - 2-23). The decimal equivalent meaning of the gain register is
D = b0 2 + b1 2
0 -1
+ b 22
-2
+ ... + bN 2
-N
=
i=0
bi2
N
-i
where the binary numbers have a value of either zero or one (b0 corresponds to the MSB). Refer to Table 4 for details.
16
DS202F3
CS5525 CS5526
Offset Register
Register
Reset (R) 2 0
-2
0
2 0
-3
2 0
-4
2 0
-5
MSB Sign
LSB 2
-20
2 0
-6
2
-19
2
-21
2
-22
2
-23
0
0
0
0
0
2-24 0
One LSB represents 2-24 proportion of the input span (bipolar span is 2 times unipolar span) Offset and data word bits align by MSB (bit MSB-4 of offset register changes bit MSB-4 of data)
Gain Register
Register
Reset (R) 2 1
0
2 0
-1
2 0
-2
2 0
-3
2 0
-4
MSB
LSB 2
-19
2 0
-5
2
-18
2
-20
2
-21
2
-22
0
0
0
0
0
2-23 0
The gain register span is from 0 to (2-2 -23). After Reset the MSB = 1, all other bits are 0. Table 3. Table 4. Offset and Gain Registers
The offset and gain calibration steps each take one conversion cycle to complete. At the end of the calibration step, the calibration control bits will be set back to logic 0, and the DF (Done Flag) bit will be set to a logic 1. For the combination self-calibration (CC2-CC0= 011; offset followed by gain), the calibration will take two conversion cycles to complete and will set the DF bit after the gain calibration is completed. The DF bit will be cleared any time the data register, the offset register, the gain register, or the setup register is read. Reading the configuration register alone will not clear the DF bit.
of the modulator are connected together and then routed to the VREF- pin as shown in Figure 11. For self-calibration of gain, the differential inputs of the modulator are connected to VREF+ and
S1 OP EN A IN + S2 C L O SE D A IN + X 20 +
Self Calibration
The CS5525/26 offer both self offset and self gain calibrations. For the self-calibration of offset in the 25 mV, 55 mV, and 100 mv ranges, the converter internally ties the inputs of the instrumentation amplifier together and routes them to the AIN- pin as shown in Figure 10. For proper self-calibration of offset to occur in the 25 mV, 55 mV, and 100 mV ranges, the AIN- pin must be at the proper common-mode-voltage (i.e. AIN- = 0V, NBV must be between -1.8 V to -2.5 V). For self-calibration of offset in the 1.0 V, 2.5 V, and 5 V ranges, the inputs
DS202F3
Figure 10. Self Calibration of Offset (Low Ranges).
S1 OPEN
A IN+
+ X20 S3 C LO S E D S2 OPEN
S4 CLO S ED
+
A INV R E F-
-
-
Figure 11. Self Calibration of Offset (High Ranges).
17
CS5525 CS5526
OPEN A IN + + X 20 A IN V RE F+ R e fe re n ce + V RE FC L O SE D C L O SE D OPEN +
E xte rnal C onnections + A IN+ 0V + A INX20 +
CM + -
Figure 12. Self Calibration of Gain (All Ranges).
Figure 13. System Calibration of Offset (Low Ranges).
VREF- as shown in Figure 12. For any input range other than the 2.5 V range, the modulator gain error can not be completely calibrated out. This is due to the lack of an accurate full scale voltage internal to the chips. The 2.5 V range is an exception because the external reference voltage is 2.5 V nominal and is used as the full scale voltage. In addition, when self-calibration of gain is performed in the 25 mV, 55 mV, and 100 mV input ranges, the instrumentation amplifier's gain is not calibrated. These two factors can leave the converters with a gain error of up to 20% after self-calibration of gain. Therefore, a system gain is required to get better accuracy, except for the 2.5 V range.
E xternal Connections + A IN+ 0V + CM + A INX20 +
Figure 14. System Calibration of Offset (High Ranges).
E xte rna l C o n ne ctio ns + + X 20 CM + A IN A IN+ Fu ll S ca le + -
System Calibration
For the system calibration functions, the user must supply the converters calibration signals which represent ground and full scale. When a system offset calibration is performed, a ground reference signal must be applied to the converter. See Figures 13 and 14. As shown in Figures 15 and 16, the user must input a signal representing the positive full scale point to perform a system gain calibration. In either case, the calibration signals must be within the specified calibration limits for each specific calibration step (refer to the System Calibration Specifications).
Figure 15. System Calibration of Gain (Low Ranges)
E xt e rna l C o n ne c tio ns + A IN + F u ll S ca le + CM + A IN X 20 +
Figure 16. System Calibration of Gain (High Ranges).
18
DS202F3
CS5525 CS5526
Assuming a system can provide two known voltages, equations can allow the user to manually compute the calibration register's values based on two uncalibrated conversions. The offset and gain calibration registers are used to adjust a typical conversion as follows: Rc = (Ru + Co>>4) * Cg / 2 23. Calibration can be performed using the following equations: Co = (Rc0/G - Ru0) << 4 Cg = 223 * G where G = (Rc1 - Rc0)/(Ru1-Ru0).
Note: Uncalibrated conversions imply that the gain and offset registers are at default {gain register = 0x800000 (Hex) and offset register = 0x000000 (Hex)}. of 20 bits. To get the equations to work correctly pad the 16 bit results with four zeros (on the right).
Calibration Tips
Calibration steps are performed at the output word rate selected by the WR2-WR0 bits of the configuration register. Since higher word rates result in conversion words with more peak-to-peak noise, calibration should be performed at lower output word rates. Also, to minimize digital noise near the devices, the user should wait for each calibration step to be completed before reading or writing to the serial port. For maximum accuracy, calibrations should be performed for offset and gain for each gain setting (selected by changing the G2-G0 bits of the configuration register). And if factory calibration is performed using the system calibration capabilities of the CS5525/26, the offset and gain register contents can be read by the system microcontroller and recorded in EEPROM. These same calibration words can then be uploaded into the offset and gain registers of the converters when power is first applied to the system, or when the gain range is changed. Two final tips include two ways to determine when calibration is complete: 1) wait for SDO to fall. It falls to logic 0 if the PF (Port Flag) bit of the configuration register is set to logic 1; or 2) poll the DF (Done Flag) bit in the configuration register which is set at completion of calibration. Whichever method is used, the calibration control bits (CC2CC0) will return to logic 0 upon completion of any calibration.
The variables are defined below.
V0 V1 Ru Ru0 Ru1 Rc Rc0 Rc1 Co Cg >> << = = = = = = = = = = = = First calibration voltage Second calibration voltage (greater than V0) Result of any uncalibrated conversion Result of uncalibrated conversion V0 (20-bit integer or 2's complement) Result of uncalibrated conversion of V1 (20-bit integer or 2's complement) Result of any conversion Desired calibration result of converting V0 (20-bit integer or 2's complement) Desired calibration result of converting V1 (20-bit integer or 2's complement) Offset calibration register value (24-bit 2's complement) Gain calibration register value (24-bit integer) The shift right operator (e.g. x >>2 is x shifted right 2 bits) The shift left operator (e.g. x<<2 is x shifted left 2 bits)
Limitations in Calibration Range
System calibration can be limited by signal headroom in the analog signal path inside the chip as discussed under the Analog Input section of this data sheet. System calibration can also be limited by the intrinsic gain errors of the instrumentation amplifier and the modulator. For gain calibrations
Note: The shift operators are used here to align the decimal points of words of various lengths. Data to the right of the decimal point may be used in the calculations shown. For the CS5525 all conversion results (Ru, Rc...) are 16 bits instead DS202F3
19
CS5525 CS5526
the input signal can be reduced to the point in which the gain register reaches its upper limit of 2.0 (decimal) [FFFFFF Hex] (this is most likely to occur with an input signal approximately 1/2 the nominal range). Alternatively, the input signal can be increased to a point in which the modulator reaches its one's density upper limit of 80% (this is most likely to occur with an input signal approximately 1.5 times the nominal range). Also, for full scale inputs larger than the nominal full scale value of the range selected, there is some voltage at which the various internal circuits may saturate due to limited amplifier headroom (this is most likely to occur on the 100 mV range setting when NBV = 1.8 V).
Serial Port Initialization
The serial port is initialized to the command mode whenever a power-on reset is performed inside the converter, when the port initialization sequence is completed, or whenever a command byte, data word sequence is completed. The port initialization sequence involves clocking 15 (or more) bytes of all 1's, followed by one byte with the following bit contents (11111110). This sequence places the chips in the command mode where it waits for a valid command.
Performing Conversions (With PF bit = 0)
Setting the SC (Single Conversion) bit of the command word to a logic 1 with the CB bit = 1, all other command bits = 0, the CS5525/CS5526 will perform one conversion. At the completion of the conversion the DF (Done Flag) bit of the configuration register will be set to a logic 1. The user can read the configuration register to determine if the DF bit is set. If DF has been set, a command can be issued to read the conversion data register to obtain the conversion data word. The DF bit of the configuration register will be cleared to logic 0 when the data register, the gain register, the offset register, or the set-up registers are read. Reading only the configuration register will not clear the DF flag bit. If an SC command is issued to the converters while they are performing a conversion, the filter will restart a convolution cycle to perform a new conversion.
Analog Output Latch Pins
The A3-A0 pins of the converters mimic the D23D20 bits of the configuration register. A3-A0 can be used to control multiplexers and other logic functions outside the converter. The outputs can sink or source at least 1 mA, but it is recommended to limit drive currents to less than 2 0 A to reduce self-heating of the chip. These outputs are powered from VA+, hence, their output voltage for a logic 1 will be limited to the VA+ voltage.
Serial Port Interface
The CS5525/26 serial interface consist of four pins, SCLK, SDO, SDI, and CS. The CS pin must be held low (logic 0) before SCLK transitions can be recognized by the port logic. The SDO output will be held at high impedance any time CS is a logic 1. If the CS pin is tied low, the port can function as a three wire interface. The SCLK input is designed with a Schmitt-trigger input to allow an optoisolator with slower rise and fall times to directly drive the pin. The SDO output is capable of sinking or sourcing up to 5 mA to directly drive an optoisolator LED. SDO will have less than a 400 mV loss in the drive voltage when sinking or sourcin g 5mA.
20
Performing Conversions (With PF bit = 1)
Setting the PF bit of the configuration register to a logic 1 enables the SDO output pin to behave as a flag signal whenever conversions are completed. This eliminates the need for the user to read the DF flag bit of the configuration register to determine if the conversion data word is available. If the SC (Single Conversion) command is issued (SC = 1, CB= 1, all other command bits = 0) the SDO pin will go low at the completion of a converDS202F3
CS5525 CS5526
sion. The user would then issue 8 SCLKs (with SDI = logic 0) to clear the SDO flag. Upon the falling edge of the 8th SCLK, the SDO pin will present the first bit (MSB) of the conversion word. 24 SCLKs (high, then low) are required to read the conversion word from the port. The user must not give an explicit command to read the conversion data register when the PF bit is set to logic 1. The data conversion word must be read before a new command can be entered (if the SC command is used with PF = 1). If the CC (Continuous Conversion) command is issued (CC = 1, CB =1, all other command bits = 0) the SDO pin will go low at the completion of a conversion. The user would then issue 8 SCLKs (with SDI = logic 0) to clear the SDO flag. Upon the falling edge of the 8th SCLK, the SDO pin will present the first bit (MSB) of the conversion word. 24 SCLKs (high, then low) are required to read the conversion word from the port. The user must not give an explicit command to read the conversion data register when the PF bit is set to logic 1. When operating in the continuous conversion mode, the user need not read every conversion. If the user does nothing after SDO falls, SDO will rise one XIN clock cycle before the next conversion word is available and then fall again to signal that another conversion word is available. If the user begins to clear the SDO flag and read the conversion data, this action must be finished before the conversion cycle which is occurring in the background is complete if the user wants to be able to read the new conversion data. To exit the continuous conversion mode, issue any valid command to the SDI input when the SDO flag falls. If a CC command is issued to the converter while it is performing a conversion, the filter will restart a convolution cycle to perform a new conversion.
Output Word Rate Selection
The WR2-WR0 bits of the configuration register set the output conversion word rate of the converters as shown in Table 2. The word rates indicated in the table assume a master clock of 32.768 kHz. Upon reset the converters are set to operate with an output word rate of 15.0 Hz.
Clock Generator
The CS5525/26 include a gate which can be connected with an external crystal to provide the master clock for the chips. They are designed to operate using a low-cost 32.768 kHz "tuning fork" type crystal. The 32.768 kHz crystal should be connected as shown in Figure 18. Lead lengths should be minimized to reduce stray capacitance. The converters will operate with an external (CMOS compatible) clock with frequencies up to three times the typical crystal frequency of 32.768 kHz. Figure 17 details the converter's performance at increased clock rates.
Figure 17. High Speed Clock Performance
The 32.768 kHz crystal is normally specified as a time-keeping crystal with tight specifications for both initial frequency and for drift over temperature. To maintain excellent frequency stability, these crystals are specified only over limited operating temperature ranges (i.e. -10 C to +60 C). However, applications with the CS5525/26 don't generally require such tight tolerances. When 32.768 kHz tuning fork crystals are used, it is recommended that protection components, an external resistor and capacitor as shown in Figure 18, be used.
DS202F3
21
CS5525 CS5526
VA+
V D+ XO UT
500 k
20 pF
C S5525 C S5526
XIN
32.768 kHz
Figure 18. Tuning Fork Crystal Connection Diagram
Digital Filter
The CS5525/26 have eight different linear phase digital filters which set the output word rates (OWRs) as stated in Table 2. These rates assume that XIN is 32.768 kHz. Each of the filters has a magnitude response similar to that shown in Figure 19. The filters are optimized to settle to full accuracy every conversion and yield better than 80 dB rejection for both 50 and 60 Hz with output word rates at or below 15.0 Hz. The converter's digital filters scale with XIN. For example with an output word rate of 15 Hz, the filter's corner frequency is typically 12.7 Hz. If XIN is increased to 64.536 kHz the OWR doubles and the filter's corner frequency moves to 25.4 Hz.
Figure 19. Filter Response (Normalized to Output Word Rate = 1)
first followed by the rest of the data bits in descending order. For the CS5525 the last byte is composed of bits D7-D4, which are always logic 1; D3-D2, which are always logic 0; and bits D1-D0 which are the two flag bits. For the CS5526 the last byte includes data bits D7-D4, D3-D2 which are always logic 0 and the two flag bits. The OF (Overrange Flag) bit is set to a logic 1 any time the input signal is: 1) more positive than positive full scale, 2) more negative than zero (unipolar mode), 3) more negative than negative full scale (bipolar mode). It is cleared back to logic 0 whenever a conversion word occurs which is not overranged. The OD (Oscillation Detect) bit is set to a logic 1 any time that an oscillatory condition is detected in the modulator. This does not occur under normal operating conditions, but may occur whenever the input
Output Coding
The CS5525/26 output data in binary format when operating in unipolar mode and in two's complement when operating in bipolar mode. The output conversion word is 24 bits, or three bytes long, as shown in Table 5. The MSB is output
Output Conversion Data CS5525 (16 bits + flags)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D8 LSB D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 0 OD OF
Output Conversion Data CS5526 (20 bits + flags)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 MSB 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D4 LSB D3 D2 D1 D0 0 0 OD OF
Table 5. Data Conversion Word
22
DS202F3
CS5525 CS5526
CS5525 16-Bit Output Coding Unipolar Input Offset Voltage Binary >(VFS-1.5 LSB) VFS-1.5 LSB FFFF FFFF ----FFFE 8000 ----7FFF 0001 ----0000 0000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB Two's Complement 7FFF 7FFF ----7FFE 0000 ----FFFF 8001 ----8000 8000 CS5526 20-Bit Output Coding Unipolar Input Offset Voltage Binary >(VFS-1.5 LSB) FFFFF VFS-1.5 LSB FFFFF ----FFFFE 80000 ----7FFFF 00001 ----00000 00000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB Two's Complement 7FFFF 7FFFF ----7FFFE 00000 ----FFFFF 80001 ----80000 80000
VFS/2-0.5 LSB
-0.5 LSB
VFS/2-0.5 LSB
-0.5 LSB
+0.5 LSB <(+0.5 LSB)
-VFS+0.5 LSB <(-VFS+0.5 LSB)
+0.5 LSB <(+0.5 LSB)
-VFS+0.5 LSB <(-VFS+0.5 LSB)
Note: VFS in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the voltage between full scale for any of the bipolar gain ranges. See text about error flags under overrange conditions. Table 6. 5525/26 Output Coding
to the converters is extremely overranged. If the OD bit is set, the conversion data bits can be completely erroneous. The OD flag bit will be cleared to logic 0 when the modulator becomes stable. Table 6 illustrates the output coding for the CS5525/26.
Power Consumption
The CS5525/26 accommodate four power consumption modes: normal, low power, standby, and sleep. The normal mode, the default mode, is entered after a power-on-reset and typically consumes 9.4 mW. The low power mode is an alternate mode that reduces the consumed power to 4.9 mW. It is entered by setting bit D16 (the low power mode bit) in the configuration register to logic 1. Since the converter's noise performance improves with increased power consumption, slightly degraded noise or linearity performance should be expected in the low power mode. The final two modes are referred to as the power save modes. They power down most of the analog portion of the chips and stop filter convolutions. The power save modes are entered whenever the PS/R bit and the CB bit of the
command word are set to logic 1. The particular power save mode entered depends on state of bit D4 (the Power Save Select bit) in the configuration register. If D4 is logic 0, the converters enters the standby mode reducing the power consumption to 1.2mW. The standby mode leaves the oscillator and the on-chip bias generator running. This allows the converters to quickly return to the normal or low power mode once the PS/R bit is set back to a logic 1. If D4 in the configuration register and CB and PS/R in the command word are set to logic 1, the sleep mode is entered reducing the consumed power to less than 500 W. Since the sleep mode disables the oscillator, approximately a 500ms oscillator start-up delay period is required before returning to the normal or low power mode.
PCB Layout
The CS5525/26 should be placed entirely over an analog ground plane with both the AGND and DGND pins of the device connected to the analog plane. Place the analog-digital plane split immediately adjacent to the digital portion of the chip.
DS202F3
23
CS5525 CS5526
PIN DESCRIPTIONS
ANALOG GROUND POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT NEGATIVE BIAS VOLTAGE LOGIC OUTPUT LOGIC OUTPUT CHARGE PUMP DRIVE CRYSTAL IN CRYSTAL OUT AGND VA+ AIN+ AINNBV A0 A1 CPD XIN XOUT
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VREF+ VOLTAGE REFERENCE INPUT VREF- VOLTAGE REFERENCE INPUT CS SDI A3 A2 SDO VD+ CHIP SELECT SERIAL DATA INPUT LOGIC OUTPUT LOGIC OUTPUT SERIAL DATA OUTPUT POSITIVE DIGITAL POWER
DGND DIGITAL GROUND SCLK SERIAL CLOCK INPUT
Clock Generator
XIN; XOUT - Crystal In; Crystal Out, Pins 9, 10. A gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock can be supplied into the XIN pin to provide the master clock for the device.
Control Pins and Serial Data I/O
CS - Chip Select, Pin 18. When active low, the port will recognize SCLK. When high the SDO pin will output a high impedance state. CS should be changed when SCLK = 0. SDI - Serial Data Input, Pin 17. SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK. SDO - Serial Data Output, Pin 14. SDO is the serial data output. It will output a high impedance state if CS = 1. SCLK - Serial Clock Input, Pin 11. A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin will recognize clocks only when CS is low. A0, A1, A2, A3 - Logic Outputs, Pin 6, 7, 15, 16. The logic states of A0-A3 mimic the states of the D20-D23 bits of the configuration register. Logic Output 0 = AGND, and Logic Output 1 = VA+.
24
DS202F3
CS5525 CS5526
Measurement and Reference Inputs
AIN+, AIN- - Differential Analog Input, Pins 3, 4. Differential input pins into the device. VREF+, VREF- - Voltage Reference Input, Pins 20, 19. Fully differential inputs which establish the voltage reference for the on-chip modulator. NBV - Negative Bias Voltage, Pin 5. Input pin to supply the negative supply voltage for the 20X gain instrumentation amplifier. May be tied to AGND if AIN+ and AIN- inputs are centered around +2.5 V; or it may be tied to a negative supply voltage (-2.1 V typical) to allow the amplifier to handle low level signals more negative than ground. CPD - Charge Pump Drive, Pin 8. Square wave output used to provide energy for the charge pump.
Power Supply Connections
VA+ - Positive Analog Power, Pin 2. Positive analog supply voltage. Nominally +5 V. VD+ - Positive Digital Power, Pin 13. Positive digital supply voltage. Nominally +3.0 V or +5 V. AGND - Analog Ground, Pin 1. Analog Ground. DGND - Digital Ground, Pin 12. Digital Ground.
DS202F3
25
CS5525 CS5526
SPECIFICATION DEFINITIONS
Linearity Error The deviation of a code from a straight line which connects the two endpoints of the A/D Converter transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in percent of full-scale. Differential Nonlinearity The deviation of a code's width from the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3/2 LSB]. Units are in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (1/2 LSB above the voltage on the AIN- pin.). When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs.
ORDERING GUIDE
Model Number CS5525-AP CS5525-AS CS5526-BP CS5526-BS Linearity Error (Max) 0.003% 0.003% 0.0015% 0.0015% Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package 20-pin 0.3" Plastic DIP 20-pin 0.2" Plastic SSOP 20-pin 0.3" Plastic DIP 20-pin 0.2" Plastic SSOP
SPITM is a trademark of Motorola Inc., MicrowireTM is a trademark of National Semiconductor Corp.
26
DS202F3
CS5525 CS5526
20 PIN PLASTIC (PDIP) PACKAGE DRAWING
D E 1 SEATING PLANE e b A A1 b1 L
TOP VIEW
c eA
SIDE VIEW
BOTTOM VIEW
INCHES DIM A A1 b b1 c D E e eA L MIN 0.155 0.020 0.015 0.050 0.008 0.960 0.240 0.095 0.300 0.125 0 MAX 0.180 0.040 0.022 0.065 0.015 1.040 0.260 0.105 0.325 0.150 15
MILLIMETERS MIN MAX 3.94 4.57 0.51 1.02 0.38 0.56 1.27 1.65 0.20 0.38 24.38 26.42 6.10 6.60 2.41 2.67 7.62 8.25 3.18 3.81 0 15
Notes: 1. Positional tolerance of leads shall be within 0 .25mm (0. 010in.) at maximum material condition, in relation to seating plane and each other. 2. Dimension eA to center of leads when formed parallel. 3. Dimension E does not include mold flash.
DS202F3
27
CS5525 CS5526
20 PIN SSOP PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e
b2 SIDE VIEW
END VIEW
SEATING PLANE
123
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.272 0.291 0.197 0.024 0.025 0 MAX 0.084 0.010 0.074 0.015 0.295 0.323 0.220 0.027 0.040 8
MILLIMETERS MIN MAX -2.13 0.05 0.25 1.62 1.88 0.22 0.38 6.90 7.50 7.40 8.20 5.00 5.60 0.61 0.69 0.63 1.03 0 8
NOTE
2,3 1 1
Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.0 7mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 a nd 0.25mm from lead tips.
28
DS202F3
CS5525 CS5526
Contacting Cirrus Logic Support
Fo r a ll pro du ct qu estio ns a nd in qu iries con tact a C irrus L og ic S ales R e pre se ntative . To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this docum ent is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obt ain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold su bject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of a ny items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this inf ormation, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated c ircuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for c reating any work for resale. An export per mit needs to be obtained from the competent authorities of the Japanese Government if any of the products or techno logies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the com petent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS M AY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEM S OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTO MER'S RISK AND CIRRUS DISCLAIMS AND M AKES NO W ARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED W ARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, W ITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE C U STOMER OR CUSTOMER'S CUSTOM ER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOM ER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EM PLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product namesin this document m ay be trademarks or service marks of their respective owners.
DS202F3
29

▲Up To Search▲

Price & Availability of CS5525-BP

	To Download CS5525-BP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .